Power Optimization techniques used in VLSI:
1] Clock gating:-
In general two kinds of power dissipation occured,one is static and the other is dynamic in nature.Static power can be negelcted.
In the above circuit,due to switching of states increase of dynamic power dissipation occurs.Dynamic power is the sum of transient power consumption and capacitive load power consumption.This can be reduced using clock gating technique which increases the overall capacitance of the clock tree.
One thing to take care is that clock gating circuits is often prone to glitches and that is why a latch has been introduced in the circuit which will take care of it.
2] Encoding Techniques:-
There are different encoding techniques which should be employed in order to reduce power.
✓Proper use of don't care encoding helps in reducing state transitions which ultimately saves power.
✓If the number of flip flops are more, number of states will also increase and hence Gray encoding should be used instead of binary encoding wherever applicable.
✓LFSR should be used wherever needed in order to reduce power.
3] UPF Based Techniques:
✓ Level Shifter:
They are specifically used when two blocks are operating in different voltages.
Commands:
set_level_shifter LS_x \
- domain y \
- applies_to outputs \
- location self/parent/other/fanout
✓ Isolation Cells:
They are used when one of the block or power domain is completely switched off to save static or dynamic power. Ex: Multiplexer
Commands:
set_isolation name
- domain name
- isolation signal
- elements list
- clamp_value
- applies-to inputs/outputs/both.
Other techniques involves Power Gating and Retention Cells.
4] SOI:-
SOI stands for Silicon on Insulator which has been used in CMOS circuits and consists of two types of insulators.One is SiO2 and the other one is sapphire and the advantage of these is the reduction of capacitance between source to body and drain to body region.
Another advantage is the reduction in diffusion capacitance which results in lower subthreshold leakage in circuits which in turn saves more power.
There are two kinds of SOI techniques available,one is PDSOI (partially depleted) and the other one is FDSOI (Fully depleted).Although FDSOI helps in reduction of tunnelling currents in CMOS but due to technology constraints PDSOI technique is widely being used.
5] Lowering DIBL:-
In short channel CMOS devices,the source and Drain comes very close to channel region and share the charge among themselves.
As the region near the Drain depletion region tend to increase,it reduces the potential barrier.
This problem is known as Drain Induced Barrier lowering and hence by reducing this,power dissipation within a CMOS Circuit can be reduced.
6] Low Power Techniques in DDR:
✓ Self Refresh
✓ Deep Power Mode
✓ Power Down
7] Supply Voltage:-
By controlling the supply voltage (VDD) or by minimising the requirement of supply voltage to a desired extent,the power dissipation within a CMOS Circuit can be minimised.
8] Operand Isolation:-
This is one of the most useful technique to reduce power dissipation.
If a circuit states are changing continuously depending on its input but as a designer we need to be concerned with the output once in some clock cycle then we can hold the input by inserting some combinational logic when the output is not being used.This process is known as operand Isolation.
✓ Self Refresh
✓ Deep Power Mode
✓ Power Down
7] Supply Voltage:-
By controlling the supply voltage (VDD) or by minimising the requirement of supply voltage to a desired extent,the power dissipation within a CMOS Circuit can be minimised.
8] Operand Isolation:-
This is one of the most useful technique to reduce power dissipation.
If a circuit states are changing continuously depending on its input but as a designer we need to be concerned with the output once in some clock cycle then we can hold the input by inserting some combinational logic when the output is not being used.This process is known as operand Isolation.
