Q)What is Verification plan? What it contains?
Ans ) Creating the real time environment for the (DUT ) to check its performance in real time. The verification plan closely tied with the hardware specification and contains a description of what features need to be verified. Contains: Directed testing Random testing Assertion Hardware and software co verificationUse of verification IP
Q)What is difference between define and parameter?
Ans) The parameter value can be changed during execution but not in the case of define construct/macros.
Q)How SV is more random stable then Verilog?
Ans:SV allows we use the CRT(constrainedrandom tests), which Verilog cannot be used. By using constrained data, we can restrict the test scenarios to those that are both valid and of interest.
Q)What are the system Verilog data types?
Ans:Logic, two state data types, Enum, typedef, struct and class. Q)What is the difference between bit[7:0] sig_1; and byte sig_2; byte is signed whereas bit [7:0] is unsigned.
Q)What is the difference between bits and logic?
Ans:bits: 2 states, default value is 0; logic: single bit, 4 states, default value is X.
Q)What data structure you used to build scoreboard?
And: Queue.
Q)What are the advantages of linkedlist over the queue?
Ans:Queue has a certain order. It's hard to insert the data within the queue. But Linked list can easily insert the data in any location.
Q)Which is best to use to model transaction? Struct or class ?
Ans:Transaction is regarded as the sequence item concept in UVM, which usually needs to have the constraint random data, thus class is more suitable for it. Struct only groups the data type but not the methods. It can be synthesized, but only used when there is complex data type.
Q)How different is the implementation of a struct and union in SV?
And:
Struct: To be able to share struct using ports and routines, you should create a type.
initial
begin
typedef struct
{int a; byte b; shortint c; int d;} my_struct_s;
my_struct_s st = '{ 32'haaaa_aaaad,8'hbb,16'hcccc,32'hdddd_dddd};
$display("str = %x %x %x %x ", st.a, st.b, st.c, st.d);
end
Union: Unlike structures, the components of a union all refer to the same location in memory. In this way, a union can be used at various times to hold different types of objects, without the need to create a separate object for each new type.
typedef union { int i; real f; } num_u; num_u un;
un.f = 0.0; // set value in floating point format.
Unions are useful when you frequently need to read and write a register in several different formats. But class is more oftenly used.
Q)What is tagged union ?
Ans:A tagged union contains an implicit member that stores a tag, which represents the name of the last union member into which a value was stored/written. If value is read from a different union member than the member into which a tagged expression value was last written, an error message will shown.
union tagged {int i;real r;} data;
data data_un;
data_un = tagged i 5; //store the 5 in data.i, and set it as the implicit tag. d_out = data_un.i; //read value
d_out = data_un.r;//ERROR: member doesn't match the union's implicit tag.
Q) What is default type of Enum data type?
And: int
Q)Which datatype is used to create user defined datatype?
And: typedef.
Ans ) Creating the real time environment for the (DUT ) to check its performance in real time. The verification plan closely tied with the hardware specification and contains a description of what features need to be verified. Contains: Directed testing Random testing Assertion Hardware and software co verificationUse of verification IP
Q)What is difference between define and parameter?
Ans) The parameter value can be changed during execution but not in the case of define construct/macros.
Q)How SV is more random stable then Verilog?
Ans:SV allows we use the CRT(constrainedrandom tests), which Verilog cannot be used. By using constrained data, we can restrict the test scenarios to those that are both valid and of interest.
Q)What are the system Verilog data types?
Ans:Logic, two state data types, Enum, typedef, struct and class. Q)What is the difference between bit[7:0] sig_1; and byte sig_2; byte is signed whereas bit [7:0] is unsigned.
Q)What is the difference between bits and logic?
Ans:bits: 2 states, default value is 0; logic: single bit, 4 states, default value is X.
Q)What data structure you used to build scoreboard?
And: Queue.
Q)What are the advantages of linkedlist over the queue?
Ans:Queue has a certain order. It's hard to insert the data within the queue. But Linked list can easily insert the data in any location.
Q)Which is best to use to model transaction? Struct or class ?
Ans:Transaction is regarded as the sequence item concept in UVM, which usually needs to have the constraint random data, thus class is more suitable for it. Struct only groups the data type but not the methods. It can be synthesized, but only used when there is complex data type.
Q)How different is the implementation of a struct and union in SV?
And:
Struct: To be able to share struct using ports and routines, you should create a type.
initial
begin
typedef struct
{int a; byte b; shortint c; int d;} my_struct_s;
my_struct_s st = '{ 32'haaaa_aaaad,8'hbb,16'hcccc,32'hdddd_dddd};
$display("str = %x %x %x %x ", st.a, st.b, st.c, st.d);
end
Union: Unlike structures, the components of a union all refer to the same location in memory. In this way, a union can be used at various times to hold different types of objects, without the need to create a separate object for each new type.
typedef union { int i; real f; } num_u; num_u un;
un.f = 0.0; // set value in floating point format.
Unions are useful when you frequently need to read and write a register in several different formats. But class is more oftenly used.
Q)What is tagged union ?
Ans:A tagged union contains an implicit member that stores a tag, which represents the name of the last union member into which a value was stored/written. If value is read from a different union member than the member into which a tagged expression value was last written, an error message will shown.
union tagged {int i;real r;} data;
data data_un;
data_un = tagged i 5; //store the 5 in data.i, and set it as the implicit tag. d_out = data_un.i; //read value
d_out = data_un.r;//ERROR: member doesn't match the union's implicit tag.
Q) What is default type of Enum data type?
And: int
Q)Which datatype is used to create user defined datatype?
And: typedef.
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