DATA TYPES
Verilog has reg and wire data-types to describe hardware behavior.
verification of hardware can become more complex and demanding, datatypes in Verilog are not sufficient to develop efficient testbenches and testcases. Hence SystemVerilog has extended Verilog by adding more C like data-types for better encapsulation and compactness.
BASIC SV Data types:
Values SystemVerilog variables can hold
String Data type
String data type in SystemVerilog is a dynamic collection of characters. Each character of the String variable is of type “byte”.
string myName = "SV";
String Methods
SystemVerilog also includes a number of special methods to work with strings. These methods use the built-in method notation. These methods are:
1. str.len() returns the length of the string, i.e., the number of characters in the string.
2. str.putc(i, c) replaces the ith character in str with the given integral value.
3. str.getc(i) returns the ASCII code of the ith character in str.
4. str.toupper() returns a string with characters in str converted to uppercase.
5. str.tolower() returns a string with characters in str converted to lowercase.
6. str.compare(s) compares str and s, and return value. This comparison is case sensitive.
7. str.icompare(s) compares str and s, and return value .This comparison is case insensitive.
SV User defined data types
Systemverilog allows the user to define datatypes.There are different ways to define user defined datatypes. They are
1.Enumarations.
2.Struct.
3.Union.
4.Typedef.
5.class
ENUM:
An enumerated type defines a set of named values. In the following example, light_1 is an enumerated variable that can store one of the three possible values (0, 1, 2). By default, the first name in the enumerated list gets the value 0 and the following names get incremental values like 1 and 2.
EX:
enum {RED, YELLOW, GREEN} light_1; // int type; RED=0,YELLOW=1,GREEN=2
enum bit[2:0] {RED, YELLOW=5, GREEN} light_2; // bit type;RED =0, YELLOW=5,GREEN =6
**Note that an enumeration name cannot start with a number !
enum {1WAY, 2TIMES, SIXPACK=6} e_formula; // Compilation error on 1WAY, 2TIMES
Enumerated type methods
SystemVerilog includes a set of specialized methods to enable iterating over the values of enumerated types.
STRUCTURES
The disadvantage of arrays is that all the elements stored in then are to be of the same data type.
If we need to use a collection of different data types, it is not possible using an array. When we require using a collection of different data items of different data types we can use a structure.
Structure is a method of packing data of different types. A structure is a convenient method of handling a group of related data items of different data types.
EX: struct {int a;byte b;bit [7:0] c;} my_data_struct;
The structured variables can be accessed using the variable name "my_data_struct".
my_data_struct.a = 123;
$display(" a value is %d ",my_data_struct.a);
UNIOUNS
Unions like structure contain members whose individual data types may differ from one another.
However the members that compose a union all share the same storage area.
A union allows us to treat the same space in memory as a number of different variables.
That is a Union offers a way for a section of memory to be treated as a variable of one type on one occasion and as a different variable of a different type on another occasion.
union {int a;byte b;bit [7:0] c;} my_data_union;
TypeDef
A typedef declaration lets you define your own identifiers that can be used in place of type specifiers such as int, byte, real. Let us see an example of creating data type "nibble".
typedef bit[3:0] nibble; // Defining nibble data type.
nibble a, b; // a and b are variables with nibble data types.
Advantages Of Using Typedef :
Shorter names are easier to type and reduce typing errors.
Improves readability by shortening complex declarations.
Improves understanding by clarifying the meaning of data.
Changing a data type in one place is easier than changing all of its uses throughout the code.
Allows defining new data types using structs, unions and Enumerations also.
Increases reusability.
Useful is type casting.
Class Data type
A class is a user-defined data type that includes data (class properties), functions and tasks that operate on data.
functions and tasks are called as methods, both are members of the class.
classes allow objects to be dynamically created, deleted, assigned and accessed via object handles.
class sv_class;
int x;// //class properties
task set(int i);// //method-1
x = i;
endtask
function int get();// //method-2
return x;
endfunction
endclass
Constant Data Types:
In SV, as per LRM definition Constants are the named data object that never changes.
SystemVerilog provide following 2 types of constants:
Elaboration time constants
Parameter constants (parameter, localparam)
Run time constants
const
Verilog has reg and wire data-types to describe hardware behavior.
verification of hardware can become more complex and demanding, datatypes in Verilog are not sufficient to develop efficient testbenches and testcases. Hence SystemVerilog has extended Verilog by adding more C like data-types for better encapsulation and compactness.
BASIC SV Data types:
Values SystemVerilog variables can hold
String Data type
String data type in SystemVerilog is a dynamic collection of characters. Each character of the String variable is of type “byte”.
string myName = "SV";
String Methods
SystemVerilog also includes a number of special methods to work with strings. These methods use the built-in method notation. These methods are:
1. str.len() returns the length of the string, i.e., the number of characters in the string.
2. str.putc(i, c) replaces the ith character in str with the given integral value.
3. str.getc(i) returns the ASCII code of the ith character in str.
4. str.toupper() returns a string with characters in str converted to uppercase.
5. str.tolower() returns a string with characters in str converted to lowercase.
6. str.compare(s) compares str and s, and return value. This comparison is case sensitive.
7. str.icompare(s) compares str and s, and return value .This comparison is case insensitive.
SV User defined data types
Systemverilog allows the user to define datatypes.There are different ways to define user defined datatypes. They are
1.Enumarations.
2.Struct.
3.Union.
4.Typedef.
5.class
ENUM:
An enumerated type defines a set of named values. In the following example, light_1 is an enumerated variable that can store one of the three possible values (0, 1, 2). By default, the first name in the enumerated list gets the value 0 and the following names get incremental values like 1 and 2.
EX:
enum {RED, YELLOW, GREEN} light_1; // int type; RED=0,YELLOW=1,GREEN=2
enum bit[2:0] {RED, YELLOW=5, GREEN} light_2; // bit type;RED =0, YELLOW=5,GREEN =6
**Note that an enumeration name cannot start with a number !
enum {1WAY, 2TIMES, SIXPACK=6} e_formula; // Compilation error on 1WAY, 2TIMES
Enumerated type methods
SystemVerilog includes a set of specialized methods to enable iterating over the values of enumerated types.
STRUCTURES
The disadvantage of arrays is that all the elements stored in then are to be of the same data type.
If we need to use a collection of different data types, it is not possible using an array. When we require using a collection of different data items of different data types we can use a structure.
Structure is a method of packing data of different types. A structure is a convenient method of handling a group of related data items of different data types.
EX: struct {int a;byte b;bit [7:0] c;} my_data_struct;
The structured variables can be accessed using the variable name "my_data_struct".
my_data_struct.a = 123;
$display(" a value is %d ",my_data_struct.a);
UNIOUNS
Unions like structure contain members whose individual data types may differ from one another.
However the members that compose a union all share the same storage area.
A union allows us to treat the same space in memory as a number of different variables.
That is a Union offers a way for a section of memory to be treated as a variable of one type on one occasion and as a different variable of a different type on another occasion.
union {int a;byte b;bit [7:0] c;} my_data_union;
TypeDef
A typedef declaration lets you define your own identifiers that can be used in place of type specifiers such as int, byte, real. Let us see an example of creating data type "nibble".
typedef bit[3:0] nibble; // Defining nibble data type.
nibble a, b; // a and b are variables with nibble data types.
Advantages Of Using Typedef :
Shorter names are easier to type and reduce typing errors.
Improves readability by shortening complex declarations.
Improves understanding by clarifying the meaning of data.
Changing a data type in one place is easier than changing all of its uses throughout the code.
Allows defining new data types using structs, unions and Enumerations also.
Increases reusability.
Useful is type casting.
Class Data type
A class is a user-defined data type that includes data (class properties), functions and tasks that operate on data.
functions and tasks are called as methods, both are members of the class.
classes allow objects to be dynamically created, deleted, assigned and accessed via object handles.
class sv_class;
int x;// //class properties
task set(int i);// //method-1
x = i;
endtask
function int get();// //method-2
return x;
endfunction
endclass
Constant Data Types:
In SV, as per LRM definition Constants are the named data object that never changes.
SystemVerilog provide following 2 types of constants:
Elaboration time constants
Parameter constants (parameter, localparam)
Run time constants
const
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