Operaters & Expressions
The SystemVerilog operators are a combination of Verilog and C operators.
In both languages, the type and size of the operands is fixed, and hence the operator is of a fixed type and size. The fixed type and size of operators is preserved in SystemVerilog.
An expression is a construct that combines operands with operators to produce a result that is a function of the values of the operands and the semantic meaning of the operator.
An operand can be one of the following:
Constant literal number, including real literals,String literal,Parameter, including local and specify parameters,Net,Net bit-select or part-select,Variable bit-select or part-select,Structure, either packed or unpacked,A call to a user-defined function, system-defined function, or method that returns any of the above.
Assignment Operators
SystemVerilog introduces the C assignment operators and special bitwise assignment operators: +=, -=, *=, /=, %=, &=, |=, ^=, <<=, >>=, <<<=, and >>>=. The assignment operator is semantically equivalent to a blocking assignment.
Increment and decrement operators
SystemVerilog includes the C increment and decrement assignment operators ++i , --i , i++ , and i-- .
These increment and decrement assignment operators behave as blocking assignments.
The increment and decrement operators, when applied to real operands, increment or decrement the operand by 1.0.
Ex:
i = 10;
j = i++ + (i = i – 1);
After execution, the value of j can be 18, 19, or 20 depending upon the relative ordering of the increment and the assignment statements.
Arithmetic operators
EX:
program main;
integer a,b;
initial
begin
b = 10;a = 22;
$display(" -(nagetion) is %0d ",-(a) );
$display(" a + b is %0d ",a+b);
$display(" a - b is %0d ",a-b);
$display(" a * b is %0d ",a*b);
$display(" a / b is %0d ",a/b);
$display(" a modulus b is %0d ",a%b);
end
endprogram
Relational operators:
An expression using these relational operators shall yield the scalar value 0 if the specified relation is false or the value 1 if it is true.
If either operand of a relational operator contains an unknown ( x ) or high-impedance ( z ) value, then the result shall be a 1-bit unknown value ( x ).
Operators are > ,>= ,<, <= .
All the relational operators shall have the same precedence. Relational operators shall have lower precedence than arithmetic operators.
Equality operators:
All four equality operators shall have the same precedence. These four operators compare operands bit for bit. As with the relational operators, the result shall be 0 if comparison fails and 1 if it succeeds.
If the operands are of unequal bit lengths, the smaller operand shall be zero-extended to thesize of the larger operand.
a === b// a equal to b, including x and z
a !== b //a not equal to b, including x and z
a == b //a equal to b, result can be unknown
a != b //a not equal to b, result can be unknown
Wildcard equality operators:
The wildcard equality operators shall have the same precedence as the equality operators.
If the operands to the wildcard equality/inequality are of unequal bit length, the operands are extended in the same manner as for the logical equality/inequality operators.
If the relation is true, the operator yields a 1. If the relation is false,it yields a 0. If the relation is unknown, it yields X .
a ==? b //a equals b, X and Z values in b act as wildcards
a !=? b a does not equal b, X and Z values in b act as wildcards
EX:
typedef enum logic [5:0] {S1=6'b100100, S2=6'b100111,S3=6'b100000} stage_e;
(stage_e ==? 6'b1??1??) would be true if stage had the value S1 or S2, and false for the value S3. If stage had the uninitialized value 6'bx, it would evaluate to false.
Logical operators:
The operators logical AND ( && ), logical OR ( || ), logical implication ( -> ), and logical equivalence ( <-> ) are logical connectives.
The result of the evaluation of a logical operation shall be 1 (defined as true), 0 (defined as false), or, if the result is ambiguous, the unknown value ( x ).
The precedence of && is greater than that of || , and both are lower than relational and equality operators.
The logical implication expression1 –> expression2 is logically equivalent to
(!expression1 || expression2) .
The logical equivalence expression1 <–> expression2 is logically equivalent to
((expression1 –> expression2) && (expression2 –> expression1)) .
Ex: If variable alpha holds the integer value 237 and beta holds the value zero, then the following examples perform as described:
regA = alpha && beta;// regA is set to 0
regB = alpha || beta;// regB is set to 1
Bitwise operators:
The bitwise operators shall perform bitwise manipulations on the operands.
The operator shall combine a bit in one operand with its corresponding bit in the other operand to calculate 1 bit for the result.
Reduction operators
The unary reduction operators shall perform a bitwise operation on a single operand to produce a single-bit result.
Shift operators:
There are two types of shift operators: the logical shift operators, << and >> , and the arithmetic shift operators, <<< and >>> .
The left shift operators, << and <<< , shall shift their left operand to the left by the number of bit positions given by the right operand.
The right shift operators, >> and >>> , shall shift their left operand to the right by the number of bit positions given by the right operand.
In both cases, the vacated bit positions shall be filled with zeros.
Ex: In this example, the variable result is assigned the binary value 0100 , which is 0001 shifted to the left two positions and zero-filled.
module shift;
logic [3:0] start, result;
initial begin
start = 1;
result = (start << 2);
end
endmodule
Conditional operator:
The conditional operator shall be right associative and shall be constructed using three operands separated by two operators in the format given in syntax.
condition ? expression1 : expression2;
Ex:(a) ? 4'b110x : 4'b1000;
If 'a' has a non-zero value then the result of this expression is 4'b110x. If 'a' is 0, then the result of this expression is 4'b1000. If 'a' is x value then the result is 4'b1x0x (this is due to the fact that the result must be calculated bit by bit on the basis of the Table)
If both expressions are real , then the resulting type is real . If one expression is real and the other expression is shortreal or integral, the other expression is cast to real , and the resulting type is real .
Concatenation operators:
A concatenation is the result of the joining together of bits resulting from one or more expressions. The concatenation shall be expressed using the brace characters { and } , with commas separating the expressions within.
Unsized constant numbers shall not be allowed in concatenations. This is because the size of each operand in the concatenation is needed to calculate the complete size of the concatenation.
The following example concatenates four expressions:
{a, b[3:0], w, 3'b101} equalent to {a, b[3], b[2], b[1], b[0], w, 1'b1, 1'b0, 1'b1}
A replication operator (also called a multiple concatenation) is expressed by a concatenation preceded by a non-negative, non- x , and non- z constant expression, called a replication constant, enclosed together within brace characters.
This example replicates w four times.
{4{w}} // yields the same value as {w, w, w, w}
OPERATOR PRECEDENCY:
() Highest precedence
++ --
& ~& | ~| ^ ~^ ~ >< -
* / %
+ -
<< >>
< <= > >=
=?= !?= == != === !==
& &~
^ ^~
| |~
&&
||
?:
= += -= *= /= %=
<<= >>= &= |= ^= ~&= ~|= ~^= Lowest precedence
The SystemVerilog operators are a combination of Verilog and C operators.
In both languages, the type and size of the operands is fixed, and hence the operator is of a fixed type and size. The fixed type and size of operators is preserved in SystemVerilog.
An expression is a construct that combines operands with operators to produce a result that is a function of the values of the operands and the semantic meaning of the operator.
An operand can be one of the following:
Constant literal number, including real literals,String literal,Parameter, including local and specify parameters,Net,Net bit-select or part-select,Variable bit-select or part-select,Structure, either packed or unpacked,A call to a user-defined function, system-defined function, or method that returns any of the above.
Assignment Operators
SystemVerilog introduces the C assignment operators and special bitwise assignment operators: +=, -=, *=, /=, %=, &=, |=, ^=, <<=, >>=, <<<=, and >>>=. The assignment operator is semantically equivalent to a blocking assignment.
Increment and decrement operators
SystemVerilog includes the C increment and decrement assignment operators ++i , --i , i++ , and i-- .
These increment and decrement assignment operators behave as blocking assignments.
The increment and decrement operators, when applied to real operands, increment or decrement the operand by 1.0.
Ex:
i = 10;
j = i++ + (i = i – 1);
After execution, the value of j can be 18, 19, or 20 depending upon the relative ordering of the increment and the assignment statements.
Arithmetic operators
EX:
program main;
integer a,b;
initial
begin
b = 10;a = 22;
$display(" -(nagetion) is %0d ",-(a) );
$display(" a + b is %0d ",a+b);
$display(" a - b is %0d ",a-b);
$display(" a * b is %0d ",a*b);
$display(" a / b is %0d ",a/b);
$display(" a modulus b is %0d ",a%b);
end
endprogram
Relational operators:
An expression using these relational operators shall yield the scalar value 0 if the specified relation is false or the value 1 if it is true.
If either operand of a relational operator contains an unknown ( x ) or high-impedance ( z ) value, then the result shall be a 1-bit unknown value ( x ).
Operators are > ,>= ,<, <= .
All the relational operators shall have the same precedence. Relational operators shall have lower precedence than arithmetic operators.
Equality operators:
All four equality operators shall have the same precedence. These four operators compare operands bit for bit. As with the relational operators, the result shall be 0 if comparison fails and 1 if it succeeds.
If the operands are of unequal bit lengths, the smaller operand shall be zero-extended to thesize of the larger operand.
a === b// a equal to b, including x and z
a !== b //a not equal to b, including x and z
a == b //a equal to b, result can be unknown
a != b //a not equal to b, result can be unknown
Wildcard equality operators:
The wildcard equality operators shall have the same precedence as the equality operators.
If the operands to the wildcard equality/inequality are of unequal bit length, the operands are extended in the same manner as for the logical equality/inequality operators.
If the relation is true, the operator yields a 1. If the relation is false,it yields a 0. If the relation is unknown, it yields X .
a ==? b //a equals b, X and Z values in b act as wildcards
a !=? b a does not equal b, X and Z values in b act as wildcards
EX:
typedef enum logic [5:0] {S1=6'b100100, S2=6'b100111,S3=6'b100000} stage_e;
(stage_e ==? 6'b1??1??) would be true if stage had the value S1 or S2, and false for the value S3. If stage had the uninitialized value 6'bx, it would evaluate to false.
Logical operators:
The operators logical AND ( && ), logical OR ( || ), logical implication ( -> ), and logical equivalence ( <-> ) are logical connectives.
The result of the evaluation of a logical operation shall be 1 (defined as true), 0 (defined as false), or, if the result is ambiguous, the unknown value ( x ).
The precedence of && is greater than that of || , and both are lower than relational and equality operators.
The logical implication expression1 –> expression2 is logically equivalent to
(!expression1 || expression2) .
The logical equivalence expression1 <–> expression2 is logically equivalent to
((expression1 –> expression2) && (expression2 –> expression1)) .
Ex: If variable alpha holds the integer value 237 and beta holds the value zero, then the following examples perform as described:
regA = alpha && beta;// regA is set to 0
regB = alpha || beta;// regB is set to 1
Bitwise operators:
The bitwise operators shall perform bitwise manipulations on the operands.
The operator shall combine a bit in one operand with its corresponding bit in the other operand to calculate 1 bit for the result.
Reduction operators
The unary reduction operators shall perform a bitwise operation on a single operand to produce a single-bit result.
Shift operators:
There are two types of shift operators: the logical shift operators, << and >> , and the arithmetic shift operators, <<< and >>> .
The left shift operators, << and <<< , shall shift their left operand to the left by the number of bit positions given by the right operand.
The right shift operators, >> and >>> , shall shift their left operand to the right by the number of bit positions given by the right operand.
In both cases, the vacated bit positions shall be filled with zeros.
Ex: In this example, the variable result is assigned the binary value 0100 , which is 0001 shifted to the left two positions and zero-filled.
module shift;
logic [3:0] start, result;
initial begin
start = 1;
result = (start << 2);
end
endmodule
Conditional operator:
The conditional operator shall be right associative and shall be constructed using three operands separated by two operators in the format given in syntax.
condition ? expression1 : expression2;
Ex:(a) ? 4'b110x : 4'b1000;
If 'a' has a non-zero value then the result of this expression is 4'b110x. If 'a' is 0, then the result of this expression is 4'b1000. If 'a' is x value then the result is 4'b1x0x (this is due to the fact that the result must be calculated bit by bit on the basis of the Table)
If both expressions are real , then the resulting type is real . If one expression is real and the other expression is shortreal or integral, the other expression is cast to real , and the resulting type is real .
Concatenation operators:
A concatenation is the result of the joining together of bits resulting from one or more expressions. The concatenation shall be expressed using the brace characters { and } , with commas separating the expressions within.
Unsized constant numbers shall not be allowed in concatenations. This is because the size of each operand in the concatenation is needed to calculate the complete size of the concatenation.
The following example concatenates four expressions:
{a, b[3:0], w, 3'b101} equalent to {a, b[3], b[2], b[1], b[0], w, 1'b1, 1'b0, 1'b1}
A replication operator (also called a multiple concatenation) is expressed by a concatenation preceded by a non-negative, non- x , and non- z constant expression, called a replication constant, enclosed together within brace characters.
This example replicates w four times.
{4{w}} // yields the same value as {w, w, w, w}
OPERATOR PRECEDENCY:
() Highest precedence
++ --
& ~& | ~| ^ ~^ ~ >< -
* / %
+ -
<< >>
< <= > >=
=?= !?= == != === !==
& &~
^ ^~
| |~
&&
||
?:
= += -= *= /= %=
<<= >>= &= |= ^= ~&= ~|= ~^= Lowest precedence
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